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integrated circuit systems, inc. ics954101 0815f?08/15/05 pin configuration recommended application: ck410 clock, intel yellow cover part output features: 2 - 0.7v current-mode differential cpu pairs 6 - 0.7v current-mode differential src pair for sata and pci-e 1 - 0.7v current-mode differential cpu/src selectable pair 6 - pci (33mhz) 3 - pciclk_f, (33mhz) free-running 1 - usb, 48mhz 1 - dot, 96mhz, 0.7v current differential pair 1 - ref, 14.318mhz key specifications: cpu outputs cycle-cycle jitter < 85ps src output cycle-cycle jitter <125ps pci outputs cycle-cycle jitter < 500ps +/- 300ppm frequency accuracy on cpu & src clocks programmable timing control hub? for desktop p4? systems functionality features/benefits: supports tight ppm accuracy clocks for serial-ata and pci-express supports spread spectrum modulation, 0 to -0.5% down spread supports cpu clks up to 400mhz uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning supports undriven differential cpu, src pair in pd# for power management. 56-pin ssop & tssop vddpci 1 56 pciclk2 gnd 2 55 pciclk1 pciclk3 3 54 pciclk0 pciclk4 4 53 fs_c/test_sel pciclk5 5 52 refout gnd 6 51 gnd vddpci 7 50 x1 itp_en/pciclk_f0 8 49 x2 pciclk_f1 9 48 vddref pciclk_f210 47sdata vdd4811 46sclk usb_48mhz 12 45 gnd gnd 13 44 cpuclkt0 dott_96mhz 14 43 cpuclkc0 dotc_96mhz 15 42 vddcpu fs_b/test_mode 16 41 cpuclkt1 vtt_pwrgd#/pd 17 40 cpuclkc1 fs_a_410 18 39 iref srcclkt1 19 38 gnda srcclkc1 20 37 vdda vddsrc 21 36 cpuclkt2_itp/srcclkt_7 srcclkt2 22 35 cpuclkc2_itp/srcclkc_7 srcclkc2 23 34 vddsrc srcclkt3 24 33 srcclkt6 srcclkc3 25 32 srcclkc6 srcclkt4_sata 26 31 srcclkt5 srcclkc4_sata 27 30 srcclkc5 vddsrc 28 29 gnd ics954101 fs_c 1 fs_b 2 fs_a 2 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 1 1 1 14.318 48.00 96.00 1. fs_c is a three-level input. please see v il_fs and v ih_fs specifications in the input/suppl y /common output parameters table for correct values. also refer to the test clarification table. 2. fs_b and fs_a are low-threshold inputs. please see the v il_fs and v ih_fs specifications in the input/suppl y /common output parameters table for correct values. reserved
2 integrated circuit systems, inc. ics954101 0815f?08/15/05 pin description pin # pin name pin type description 1 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 2 gnd pwr ground p in. 3 pciclk3 out pci clock out p ut. 4 pciclk4 out pci clock out p ut. 5 pciclk5 out pci clock out p ut. 6 gnd pwr ground p in. 7 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 8 itp_en/pciclk_f0 i/o free runnin g pci clock not affected by pci_stop#. itp_en: latched input to select pin functionality 1 = cpu_itp pair 0 = src p air 9 pciclk_f1 out free runnin g pci clock not affected b y pci_stop# . 10 pciclk_f2 out free runnin g pci clock not affected b y pci_stop# . 11 vdd48 pwr power p in for the 48mhz out p ut.3.3v 12 usb_48mhz out 48.00mhz usb clock 13 gnd pwr ground p in. 14 dott_96mhz out true clock of differential p air for 96.00mhz dot clock. 15 dotc_96mhz out com p lement clock of differential p air for 96.00mhz dot clock. 16 fs_b/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 17 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks, plls and the cr y stal oscillator are sto pp ed. 18 fs_a_410 in 3.3v tolerant low threshold input for cpu frequency selection. this pin requires ck410 fsa. refer to input electrical characteristics for vil_fs and vih_fs threshold values. 19 srcclkt1 out true clock of differential src clock p air. 20 srcclkc1 out com p lement clock of differential src clock p air. 21 vddsrc pwr su pp l y for src clocks, 3.3v nominal 22 srcclkt2 out true clock of differential src clock p air. 23 srcclkc2 out com p lement clock of differential src clock p air. 24 srcclkt3 out true clock of differential src clock p air. 25 srcclkc3 out com p lement clock of differential src clock p air. 26 srcclkt4_sata out true clock of differential src/sata p air. 27 srcclkc4_sata out com p lement clock of differential src/sata p air. 28 vddsrc pwr supply for src clocks, 3.3v nominal
3 integrated circuit systems, inc. ics954101 0815f?08/15/05 pin description (continued) pin # pin name type description 29 gnd pwr ground p in. 30 srcclkc5 out com p lement clock of differential src clock p air. 31 srcclkt5 out true clock of differential src clock p air. 32 srcclkc6 out com p lement clock of differential src clock p air. 33 srcclkt6 out true clock of differential src clock p air. 34 vddsrc pwr su pp l y for src clocks, 3.3v nominal 35 cpuclkc2_itp/srcclkc_7 out complimentary clock of cpu_itp/src differential pair cpu_itp/src output. these are current mode outputs. external resistors are required for volta g e bias. selected b y itp_en in p ut. 36 cpuclkt2_itp/srcclkt_7 out true clock of cpu_itp/src differential pair cpu_itp/src output. these are current mode outputs. external re sistors are required for voltage bias. selected b y itp_en in p ut. 37 vdda pwr 3.3v p ower for the pll core. 38 gnda pwr ground p in for the pll core. 39 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate cu rrent. 475 ohms is the standard value. 40 cpuclkc1 out complimentary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 42 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 43 cpuclkc0 out complimentary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 44 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 45 gnd pwr ground p in. 46 sclk in clock p in of smbus circuitr y , 5v tolerant. 47 sdata i/o data p in for smbus circuitr y , 5v tolerant. 48 vddref pwr ref, xtal p ower su pp l y , nominal 3.3v 49 x2 out cr y stal out p ut, nominall y 14.318mhz 50 x1 in cr y stal in p ut, nominall y 14.318mhz. 51 gnd pwr ground p in. 52 refout out reference clock out p ut 53 fs_c/test_sel in 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values. test_sel: 3-level latched input to enable test mode. refer to test clarification table 54 pciclk0 out pci clock out p ut. 55 pciclk1 out pci clock out p ut. 56 pciclk2 out pci clock output.
4 integrated circuit systems, inc. ics954101 0815f?08/15/05 ics954101 follows intel ck410 yellow cover specification. this clock synthesizer provides a single chip solution for next generation p4 intel processors and intel chipsets. ics954101 is driven with a 14.318mhz crystal. it generates cpu outputs up to 400mhz. it also provides a tight ppm accuracy output for serial ata and pci-express support. general description block diagram power groups vdd gnd 48 51 xtal, ref 1,7 2,6 pciclk outputs 21,28,34 29 srcclk outputs 37 38 master clock, cpu analog 11 13 dot, usb, pll_48 42 45 cpuclk clocks description pin number i ref pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz, usb x1 x2 xtal sdata sclk v tt_pwrgd#/pd fs_a fs_b fs_c itp_en test_mode test_sel control logic refout cpuclkt (2:0) cpuclkc (2:0) srcclkt (7:1) srcclkc (7:1) pciclk (5:0) pciclkf (2:0) 96mhz_dott_0 96mhz_dotc_0
5 integrated circuit systems, inc. ics954101 0815f?08/15/05 general i 2 c serial interface information for the ics954101 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
6 integrated circuit systems, inc. ics954101 0815f?08/15/05 absolute max symbol parameter min max units vdd_a 3.3v core supply voltage v dd + 0.5v v vdd_in 3.3v logic input supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot input e s d protection human body model 2000 v electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v input high current i ih v in = v d d -5 5 ua i il1 v in = 0 v; inputs with no pull- up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua low threshold input high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v low threshold input low volta g e v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v operating supply current i dd3. 3op 3.3 v +/-5%, full load 350 500 ma all diff pairs driven 70 ma all differential pairs tri-stated 12 ma input frequency 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1,2 modulation frequency trian g ular modulation 30 33 khz 1 tdrive_pd# cpu output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 smbus voltage v d d 2.7 5.5 v 1 low-level output voltage v olsmbus @ i pullup 0.4 v 1 c urrent sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 see timin g dia g rams for timin g requirements. 3 input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm accuracy on pll outputs. input low current powerdown current i dd3.3pd input capacitance 1
7 integrated circuit systems, inc. ics954101 0815f?08/15/05 electrical characteristics - cpu 0. 7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max volta g evovs 1150 1 min volta g evuds -300 1 crossin g volta g e ( abs ) vcross ( abs ) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz s p read 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz s p read 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz s p read 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz s p read 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz s p read 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz s p read 7.4978 5.4000 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 400mhz nominal/s p read 2.4143 ns 1,2 333.33mhz nominal/s p read 2.9141 ns 1,2 266.66mhz nominal/s p read 3.6639 ns 1,2 200mhz nominal/s p read 4.8735 ns 1,2 166.66mhz nominal/s p read 5.8732 ns 1,2 133.33mhz nominal/s p read 7.3728 ns 1,2 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 cpu (1:0) v t = 50% 100 ps 1 skew t sk4 cpu (1:0) to cpu_itp, v t = 50% 150 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 85 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout p ut is at 14.31818mhz t absmin absolute min period statistical measurement on single ended signal using oscilloscope math function. mv measurement on sin g le ended signal using absolute value. mv average period tperiod
8 integrated circuit systems, inc. ics954101 0815f?08/15/05 electrical characteristics - src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , ref = 475 ? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 850 1 volta g e low vlow -150 150 1 max volta g evovs 1150 1 min volta g e vuds -300 1 crossing voltage (abs) vcross(abs) 250 350 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1 lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 absolute min p eriod tabsmin 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 src(7:0), v t = 50% 250 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout p ut is at 14.31818mhz mv measurement on single ended signal using absolute value. mv average period tperiod statistical measurement on single ended signal using oscilloscope
9 integrated circuit systems, inc. ics954101 0815f?08/15/05 electrical characteristics - pciclk/pciclk_f t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y ppm see tperiod min-max values -300 300 ppm 1,2 33.33mhz output nominal 29.99100 30.00900 ns 2 33.33mhz output spread 29.99100 30.15980 ns 2 33.33mhz output nominal 29.49100 30.50900 ns 2 33.33mhz output spread 29.49100 30.65980 ns 2 clk high time t h1 12 n/a ns 1 clock low time t l1 12 n/a ns 1 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 500 ps 1 1 guaranteed by design, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refoutput is at 14.31818mhz output low current i ol absolute min/max clock period t abs clock period t period output high current i oh electrical characteristics - usb_48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 48.0000mhz output nominal 20.82570 20.83400 ns 2 absolute min/max clock period t abs nominal 20.48125 21.18542 ns 2 clk high time t h1 8.094 10.036 ns 1 clock low time t l1 7.694 9.836 ns 1 v oh @ min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma edge rate rising edge rate 1 2 v/ns 1 edge rate falling edge rate 1 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.4 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.3 2 ns 1 duty cycle d t1 v t = 1.5 v 454855 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 1 1 guaranteed by design, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refoutput is at 14.31818mhz output low current i ol output high current i oh
10 integrated circuit systems, inc. ics954101 0815f?08/15/05 electrical characteristics - dot, 96mhz 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source out p ut im p edance zo v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 850 1 volta g e low vlow -150 150 1 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossing voltage ( abs ) vcross(abs) 250 550 mv 1 crossing voltage ( var ) d-vcross variation of crossing over all ed g es 140 mv 1 long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 avera g e period tperiod 96.00mhz nominal 10.4135 10.4198 ns 2 absolute min period tabsmin 96.00mhz nominal 10.1635 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 250 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout p ut is at 14.31818mhz measurement on single ended signal using mv statistical measurement on single ended signal mv
11 integrated circuit systems, inc. ics954101 0815f?08/15/05 electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y ppm see tperiod min-max values -300 300 ppm 1 clock period t p eriod 14.318mhz output nominal 69.82700 69.85500 ns 1 absolute min/max clock period t abs nominal 68.82033 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1 1 guaranteed b y desi g n, not 100% tested in production.
12 integrated circuit systems, inc. ics954101 0815f?08/15/05 i 2 c table: read-back register pin # nam e control function t yp e0 1 pwd bit 7 cpuclk2/rcclk7 enable output enable rw disable enable 1 bit 6 srcclk6 enable output enable rw disable enable 1 bit 5 srcclk5 enable output enable rw disable enable 1 bit 4 srcclk4 enable output enable rw disable enable 1 bit 3 srcclk3 enable output enable rw disable enable 1 bit 2 srcclk2 enable output enable rw disable enable 1 bit 1 srcclk1 enable output enable rw disable enable 1 bit 0 i 2 c table: spreading and device behavior control register pin # nam e control function t yp e0 1 pwd bit 7 pci_f0 enable output enable rw disable enable 1 bit 6 dot_96mhz output enable rw disable enable 1 bit 5 usb_48mhz enable output enable rw disable enable 1 bit 4 refout enable output enable rw disable enable 1 bit 3 1 bit 2 cput1/cpuc1 output enable rw disable enable 1 bit 1 cput0/cpuc0 output enable rw disable enable 1 bit 0 spread spectrum mode spread off rw spread off spread on 0 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 pciclk5 output enable rw disable enable 1 bit 6 pciclk4 output enable rw disable enable 1 bit 5 pciclk3 out p ut enable rw disable enable 1 bit 4 pciclk2 out p ut enable rw disable enable 1 bit 3 pciclk1 out p ut enable rw disable enable 1 bit 2 pciclk0 output enable rw disable enable 1 bit 1 pci_f2 enable output enable rw disable enable 1 bit 0 pci_f1 enable output enable rw disable enable 1 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 cpu_itp/srcclk7 rw free-running stoppable 0 bit 6 srcclk6 rw free-runnin g stoppable 0 bit 5 srcclk5 rw free-running stoppable 0 bit 4 srcclk4 rw free-runnin g stoppable 0 bit 3 srcclk3 rw free-running stoppable 0 bit 2 srcclk2 rw free-runnin g stoppable 0 bit 1 srcclk1 rw free-running stoppable 0 bit 0 0 54 4 3 56 55 30,31 26,27 32,33 9 b y te 0 35,36 32,33 30,31 26,27 24,25 22,23 19,20 b y te 2 5 10 24,25 22,23 19,20 - 43,44 - 40,41 12 52 b y te 3 free-running control default: not affected by pci/src_stop (byte 6, bit 3) reserved reserved - b y te 1 54 14,15 reserved 35,35
13 integrated circuit systems, inc. ics954101 0815f?08/15/05 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 1 bit 6 dot_96mhz driven in pd rw driven hi-z 1 bit 5 pci_f2 rw free-runnin g stoppable 1 bit 4 pci_f1 rw free-running stoppable 1 bit 3 pci_f0 rw free-runnin g stoppable 1 bit 2 1 bit 1 1 bit 0 1 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 src stop drive mode drive mode in pci_stop rw driven hi-z 0 bit 6 0 bit 5 0 bit 4 0 bit 3 src pd drive mode drive mode in pd rw driven hi-z 0 bit 2 cpuclk_itp drive mode in pd rw driven hi-z 0 bit 1 cpuclk1 drive mode in pd rw driven hi-z 0 bit 0 cpuclk0 drive mode in pd rw driven hi-z 0 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 test mode selection test mode selection rw hi-z ref/n 0 bit 6 test clock mode entry test mode rw disable enable 0 bit 5 0 bit 4 refout stren g th stren g th pro g rw 1x 2x 1 bit 3 pci/src_stop stop all pci and src clocks rw enabled, all stoppable pci and src clocks are stopped. disabled, all stoppable pci and src clo cks are running 1 bit 2 fs_c readback r - - latched bit 1 fs_b readback r - - latched bit 0 fs_a readback r - - latched i 2 c table: vendor & revision id register pin # nam e control function t yp e0 1 pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 - - reserved - vendor id - - - b y te 7 - revision id reserved - - 40,41 43,44 52 - - - 17,18,19,20,22,23, 24,25,26,27,30,31, 32,33,35,36 54,55,56,3,4,5,8,9, 10 19,20,22,23, 24,25,26,27,30,31, 32,33,35,36 35,36 reserved reserved 10 9 8 reserved reserved reserved free-running control not affected by reserved b y te 4 - b y te 5 b y te 6 19,20,22,23, 24,25,26,27,30,31, 32,33,35,36 14,15 -
14 integrated circuit systems, inc. ics954101 0815f?08/15/05 test clarification table comments fs_c/test_ sel hw pin fs_b/test_ mode hw pin test entry bit b6b6 ref/n or hi-z b6b7 output 0x0xnormal 10x0hi-z 10x1ref/n 11x0ref/n 11x1ref/n 0x10hi-z 0x11ref/n b6b6: 1= enter test mode, default = 0 (normal operation) b6b7: 1= ref/n, default = 0 (hi-z) hw sw fs_c/test_sel is a 3-level latched input. o power-up w/ v >= 2.0v to select test o power-up w/ v < 2.0v to have pin function as fs_c. when pin is fs_c, vih_fs and vil_fs levels apply. fs_b/test_mode is a low-threshold input o vih_fs and vil_fs levels apply. o test_mode is a real time input test_sel can be invoked after power up through smbus b6b6. o if test is selected by b6b6, only b6b7 controls test_mode. the fs_b/test_mode pin is not used. power must be cycled to exit test.
15 integrated circuit systems, inc. ics954101 0815f?08/15/05 min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a0808 variations min max min max 56 18.31 18.55 .720 .730 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d (inch) symbol see variations see variations index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l ordering information ics954101 y flft example: designation for tape and reel packaging rohs compliant (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) prefix ics, av = standard device ics xxxx y f lf t
16 integrated circuit systems, inc. ics954101 0815f?08/15/05 in d ex a r ea in d ex a r ea 1 2 1 2 n d e1 e s eatin g p lane s eatin g p lane a1 a a 2 a 2 e - c - - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10-0039 56-lead 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, m o-153 ordering information ics954101 y glft example: designation for tape and reel packaging rohs compliant (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) prefix ics, av = standard device ics xxxx y g lf t
17 integrated circuit systems, inc. ics954101 0815f?08/15/05 revision history rev. issue date description page # e 6/1/2005 1. updated block diagram. 2. update lf orderin g information to rohs compliant. 4,15-16 f 0815/05 1. removed skew from ref electrical characteristics table - onl y 1 ref output. 11
document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military global sites email | print contact idt | investors | press search entire site home > products > timing solutions > pc-notebook-server clocks > clock synthesizer by chipset vendor > desktop chipsets > 954101 a dd to m y idt [ ? ] 954101 (desktop chipsets) description grantsdale - ck410 clock, intel yellow cover part market group pc clock additional info ics954101 follows intel ck410 yellow cover spec ification. this clock sy nthesizer provides a singl e chip solution for next gener ation p4 intel processors and intel chipsets. ic s954101 is driven with a 14.318mhz crystal. it generates cpu output s up to 400mhz. it also pro vides a tight ppm accuracy output for serial ata and pci-expr ess support ? supports tight ppm accuracy clocks for serial-ata and ? pci-express ? supports spread spectrum modulation, 0 to -0.5% dow n spread ? supports cpu clks up to 400mhz ? uses external 14.318mhz crystal, external crystal load caps are required for frequency tuni ng ? supports undriven differential cp u, src pair in pd# er management. you may also like... related orderable parts attributes 954101DFLF 954101DFLFt 954101dglf 954101dglft voltage 3.3 v (pvg56) 3.3 v (pvg56) 3.3 v (pag56) 3.3 v (pag56) package ssop 56 ssop 56 tssop 56 tssop 56 speed na na na na temperature c c c c status active active active active sample yes no yes no minimum order quantity 130 1000 102 1000 factory order increment 26 1000 34 1000 related documents type title size revision date datasheet 954101 datasheet 189 kb 03/27/2006 model - ibis 954101 ibis model 237 kb 03/27/2006 pa g e 1 of 2 08-jun-2007 mhtml:file://c:\954101.mh t
node: www.idt.com home | site map | about idt | press room | investor relations | trademark | privacy policy | careers | register | contact us use of this website signifies your agreement to the acceptable use and privacy policy . copyright 1997-2007 integrated device technology, inc. all rights reserved. pa g e 2 of 2 08-jun-2007 mhtml:file://c:\954101.mh t
document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military global sites email | print contact idt | investors | press search entire site home > products > timing solutions > pc-notebook-server clocks > clock synthesizer by chipset vendor > desktop chipsets > 954101 a dd to m y idt [ ? ] 954101 (desktop chipsets) description grantsdale - ck410 clock, intel yellow cover part market group pc clock additional info ics954101 follows intel ck410 yellow cover spec ification. this clock sy nthesizer provides a singl e chip solution for next gener ation p4 intel processors and intel chipsets. ic s954101 is driven with a 14.318mhz crystal. it generates cpu output s up to 400mhz. it also pro vides a tight ppm accuracy output for serial ata and pci-expr ess support ? supports tight ppm accuracy clocks for serial-ata and ? pci-express ? supports spread spectrum modulation, 0 to -0.5% dow n spread ? supports cpu clks up to 400mhz ? uses external 14.318mhz crystal, external crystal load caps are required for frequency tuni ng ? supports undriven differential cp u, src pair in pd# er management. you may also like... related orderable parts attributes 954101DFLF 954101DFLFt 954101dglf 954101dglft voltage 3.3 v (pvg56) 3.3 v (pvg56) 3.3 v (pag56) 3.3 v (pag56) package ssop 56 ssop 56 tssop 56 tssop 56 speed na na na na temperature c c c c status active active active active sample yes no yes no minimum order quantity 130 1000 102 1000 factory order increment 26 1000 34 1000 related documents type title size revision date datasheet 954101 datasheet 189 kb 03/27/2006 model - ibis 954101 ibis model 237 kb 03/27/2006 pa g e 1 of 2 08-jun-2007 mhtml:file://c:\954101.mh t
node: www.idt.com home | site map | about idt | press room | investor relations | trademark | privacy policy | careers | register | contact us use of this website signifies your agreement to the acceptable use and privacy policy . copyright 1997-2007 integrated device technology, inc. all rights reserved. pa g e 2 of 2 08-jun-2007 mhtml:file://c:\954101.mh t

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